1. Technical Field
Methods for deuterium sintering in fabricating integrated circuits, e.g., CMOS and biCMOS processes, are disclosed herein. More particularly, methods for deuterium sintering at high temperatures prior to depositing a metallization layer on a partially fabricated integrated circuit are disclosed.
2. Background of Related Art
Performance degradation of semiconductor devices that occurs with time, which is often referred to as the hot carrier (electron or hole) degradation effect, is well known. It is believed that this efficiency degradation is caused by defects that are generated by the current flow through the device. It is believed that these defect states reduce the mobility and lifetime of the carriers and cause degradation in performance of the device.
In most cases, the device includes at least a substrate comprised of silicon and a dielectric layer deposited on at least a portion of the substrate to form substrate/dielectric interfaces and the defects are thought to be caused by dangling bonds (i.e., unsaturated silicon bonds) that introduce states in the energy gap, which remove charge carriers or add unwanted charge carriers in the device, depending in part on the applied bias. While dangling bonds occur primarily at surfaces or interfaces in the device, they also are thought to occur at vacancies, micropores, dislocations, and are also thought to be associated with impurities. To alleviate the problems caused by such dangling bonds, a hydrogen passivation process has been adopted and has become a well-known and established practice in the fabrication of such devices. See, e.g., U.S. Pat. Nos. 3,849,204; 3,923,559; 4,113,514; 4,151,007; and 5,711,998.
In the hydrogen passivation process, it is thought that the defects that affect the operation of semiconductor devices are removed when hydrogen bonds with the silicon at the dangling bond sites. While hydrogen passivation eliminates the immediate problem associated with these dangling bonds, it does not eliminate degradation permanently. Rather, hydrogen atoms added by the passivation process can be xe2x80x9cdesorbedxe2x80x9d or removed from the previous dangling bond sites by radiation or by the xe2x80x9chot carrier effect.xe2x80x9d
In general, a hot carrier is an electron or hole that obtains a high kinetic energy when voltages are applied to the electrodes of the device. Under such operating conditions, the hydrogen atoms, which were added by the hydrogen passivation process, are knocked off by the hot electrons. This results in aging or degradation of the device""s performance. According to established theory, this aging process occurs as the result of hot carriers stimulating the desorption of hydrogen from the surface of the silicon substrate or the SiO2 interface. While dangling bonds occur primarily at the surfaces or interfaces in the device, they are also believed to occur at vacancies, micropores, dislocations and also to be associated with impurities.
This hot carrier effect is particularly of concern with respect to smaller devices in which proportionally larger voltages are used. When such high voltages are used, channel carriers can degrade device behavior. For example, in silicon-based P-channel MOSFETs, channel strength can be reduced by trapped energetic holes in the oxide which lead to a positive oxide charge near the drain. On the other hand, in N-channel MOSFETs, gate-2-drain shorts may be caused by electrons entering the oxide and creating interface traps and oxide wear-out. xe2x80x9cDrain engineeringxe2x80x9d has been an emerging field attempting to cope with these problems, for example involving the use of a lightly-doped drain (LDD) in which a lightly-doped extension of the drain is created between the channel and the drain proper. Such solutions are, however, expensive because they typically complicate the fabrication process. Their avoidance, or at least their simplification, would be desirable.
One approach used to address the above-discussed hot carrier aging problem involves employing, in lieu of hydrogen, an isotope of hydrogen, e.g., deuterium, to passivate the substrate/dielectric interfaces. However, passivation with deuterium instead of hydrogen will typically occur at the back end of the semiconductor device fabrication process, that is, after the metallization layer is deposited on at least the dielectric layers formed on the semiconductor substrate. See, e.g., U.S. Pat. No. 6,071,751. One problem associated with this passivation process is that since deuterium is a larger molecule than hydrogen, it does not diffuse rapidly through the dielectric layers thereby resulting in substantially no hot carrier aging improvement. As a result, any excess hydrogen in the various dielectric layers redistributes thus achieving mainly hydrogen passivation of the substrate/dielectric interfaces.
It would be advantageous to introduce hydrogen isotopes, such as, for example, deuterium, at the front end of the semiconductor device fabrication process, i.e., before formation of a metallization layer, by introducing the isotopes into a partially fabricated semiconductor structure containing at least a semiconductor substrate and a dielectric layer formed on a portion of the substrate to form substrate/dielectric interfaces wherein the dielectric layer contains at least one conductive material via plug formed therein to provide improved hot carrier aging in the resulting semiconductor device.
A novel method in fabricating an integrated circuit employing a front end deuterium sintering step has been discovered. The method includes at least providing a partially fabricated integrated circuit structure having a top surface, the structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein; and, sintering the structure in the presence of a fluid comprising deuterium-containing components prior to a metallization layer being deposited on the structure. Optionally, the deuterium sintered structure can be quenched and then subjected to a back end deuterium sintering step.
In a particularly useful embodiment, the method includes the steps of:
a) providing a partially fabricated integrated circuit structure having a top surface, the structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein;
b) sintering the structure in the presence of a first fluid comprising deuterium-containing components at a first temperature prior to a metallization layer being deposited on the structure;
c) depositing at least a metallization layer on at least a portion of the sintered structure; and,
d) sintering the structure in the presence of a second fluid comprising deuterium-containing components at a second temperature.
Methods of the invention and devices formed therefrom provide unique advantages in the field of semiconductor devices, their preparation and their use. For example, the resulting device demonstrates improved operational characteristics and resist aging or xe2x80x9cdepassivationxe2x80x9d due to hot-carrier effects. Moreover, the resulting devices formed from the methods of the invention can be operated using higher voltages to increase performance, while better resisting degradation due to hot-carrier effects. Likewise, methods of the invention are beneficial for preparing radiation hard devices, which are usually operated at higher voltages. Further, methods of the invention can be readily and economically practiced and incorporated into existing fabrication techniques, and may eliminate the need for costly and/or complicated measures otherwise taken to guard against hot electron effects, for example, lightly doped drain (LDD) technology, or provide more processing flexibility in the conduct of such measure.